This invention relates to circuitry for translating TTL signals to ECL-compatible signals and, more particularly, relates to a TTL-to-ECL converter that produces ECL-compatible waveforms with a minimum of distortion over a predetermined temperature range.
Hybrid logic circuits that combine two or more conventional logic families in a single integrated circuit have been widely considered in the prior art. For example, U.S. patent application No. 642,756, filed on Aug. 21, 1984, now U.S. Pat. No. 4,684,831, issued Aug. 4, 1987 and assigned to the assignee of this patent application, describes a family of hybrid logic circuitry which mixes high-speed linear logic, such as ECL, with digital circuitry, such as TTL, to provide the ability to custom design logic systems. As stated in the referenced patent application, the reason for combining logic families in a single monolithic IC is to wed the operational speed of the emitter-coupled logic with the noise tolerance and relatively low power consumption of saturated logic such as TTL.
One example of the integration of the two logic families into a single logic array is the Q700 logic array family available from Applied Micro Circuits Corporation, San Diego, Calif., the assignee of this patent application.
As is known, the interface between different logic families in a hybrid logic IC requires translation of, for example, TTL logic signal levels to the signal levels of a linear logic family such as ECL. This requirement is well-known and can be understood with reference, for example, to the background section of Yang et al. U.S. Pat. No. 4,533,842. As stated in the Yang patent, a primary design goal for such a converter is to perform the signal level conversion over the military temperature range (-55.degree. C. to 125.degree. C.).
The Yang patent presents a design for stabilizing the operation of a TTL-to-ECL converter over the specified military temperature range. However, a major drawback of the class of prior art TTL-to-ECL converters represented by the Yang patent is that the temperature sensitivity they are designed to avoid resides in a buffer portion interfacing the TTL and ECL portions of the converter. What has not yet been realized regarding such prior art converters is that the buffer, whether temperature-compensated or not, itself imposes a significant degradation in the operation of the converter. This damaging effect can be understood with reference to FIG. 1.
In the prior art converter of FIG. 1, a pair of emitter-coupled transistors Q.sub.1 and Q.sub.2 are connected to an emitter current source transistor Q.sub.3. The level of current switched between the transistors Q.sub.1 and Q.sub.2 is determined by the magnitude of the voltage V.sub.CS, applied to the base of the current source transistor Q.sub.3. The base of the emitter Q.sub.2 is connected to a threshold voltage V.sub.T that establishes a switching level against which the pair of transistors Q.sub.1 and Q.sub.2 compare a TTL signal provided through an input node I. The TTL input signal is buffered through a buffering circuit consisting of D.sub.1, D.sub.2, and R.sub.1. The buffered TTL signal is connected to the base of Q.sub.1 and causes the current generated by the transistor Q.sub.3 to be switched to either Q.sub.1 or Q.sub.2, depending upon the relationship of the level of the buffered TTL signal to the threshold voltage V.sub.T. As is conventional, if the buffered TTL signal level is higher than V.sub.T, Q.sub.1 is turned on to fully conduct the emitter current. When the level of the buffered TTL signal falls below V.sub.T, the transistor Q.sub.2 is turned on to conduct all of the emitter current. The transistors Q.sub.4 and Q.sub.5 are emitter followers working with resistors R.sub.4 and R.sub.5, respectively, to provide low impedance drive for the complementary outputs O and O of the converter.
The improvement to the circuit of FIG. 1 represented by the Yang patent consists of the provision of a band gap voltage generator 12 to provide a threshold voltage V.sub.T that is stabilized with respect to temperature in order to maintain a reliable threshold against which the transistor pair Q.sub.1 and Q.sub.2 switch in response to the buffered TTL signal. Yang provides a temperature dependency in V.sub.T that works against and cancels a temperature dependency in the input buffer diode D.sub.1. Thus, there is implicit in this improvement the admission that the input buffer can negatively affect the operation of the FIG. 1 converter.
In fact, the buffer section of the FIG. 1 converter imposes several other shortcomings on the operation of the converter. The pull-up resistor R.sub.1 usually has a value in the range of 10K-15K ohms in order to maintain a low current level through the node I when the TTL signal is in a low state. However, the presence of R.sub.1 imposes a long time constant during the low-to-high transition, thereby slowing the current switchover between the transistors Q.sub.2 and Q.sub.1 and lengthening the rise time of the positive-sense ECL signal at node O. When the TTL signal takes a high-to-low transition, the switch in conduction from transistor Q.sub.1 to Q.sub.2 is faster, since the current path extends through D.sub.1, D.sub.2, and the base-to-emitter junction of Q.sub.2. The result is nonsymmetry and distortion between the positive and negative excursions of the ECL signal.
The presence of the buffer between the TTL circuit feeding the input node I and the emitter-coupled transistor pair Q.sub.1 and Q.sub.2 also imposes a delay in the process of converting from TTL to ECL signal formats. This naturally reduces the speed of any process depending upon the conversion.
Further, the two critical reference voltages in the FIG. 1 converter, that is V.sub.CS and V.sub.T, are generated from different sources, with V.sub.CS being produced by a reference voltage generator 14. Since different sources are used to generate the voltages, it is difficult to make the voltages react in exactly the same way to a dynamic environment, which contributes further distortion to the converted waveform.